JSSC 2015第5期Other

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

针对64 Mb和128 Mb链式FeRAM的高可靠性参考位线偏置设计，通过改进带隙基准电路和电梯电路，显著提升信号窗口。

信号窗口提升22 mV（64 Mb）和40 mV（128 Mb），工作电压范围1.5 V ±0.2 V

FeRAM参考位线偏置带隙基准电路电梯电路信号窗口

▸改进带隙基准电路，配备3位温度系数调节器和6位DAC

▸新型电梯电路，补偿温度变化和阵列工作电压波动

▸利用铁电熔丝实现低外部VDD下的温度依赖性控制

Abstract

This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelect ric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0” data. The reference bitline bias of 64 Mb chip is designed to keep inter- mediate value of “1” and “0” data at any operating temperatures from Ct o8 5 C by introducing a modiﬁed band-gap refer- ence circuit with 3 bit temperature coefﬁcient trimmers and 6