Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs Ryu Ogiwara

Abstract

This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelect ric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0” data. The reference bitline bias of 64 Mb chip is designed to keep inter- mediate value of “1” and “0” data at any operating temperatures from Ct o8 5 C by introducing a modified band-gap refer- ence circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the “ele- vator circuit” with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array op- erating voltage V AA fluctuation as well as temperature var iation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage V AA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VA A .