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A 0003 mm 10 b 240 MSs 07 mW SAR ADC in 28 nm CMOS With Digital Error Correction
本文提出了一种28nm CMOS工艺下的10位240MS/s SAR ADC，采用数字误差校正和DAC切换技术提升性能。
28nm CMOS, 1V, 240MS/s
SAR ADC数字误差校正DAC切换技术比较器低功耗
▸基于非二进制搜索的数字误差校正技术
▸提升比较器输入共模电压的切换方案
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Abstract
This paper describes a single-channel, calibra-
tion-free Successive-Approximation-Register (SAR) ADC with a
resolution of 10 bits at 240 MS/s. A DAC switching technique and
an addition-only digital error c orrection technique based on the
non-binary search are proposed to tackle the static and dynamic
non-idealities attributed to capacitor mismatch and insufficient
DAC settling. The conversion s peed is enhanced, and the power
and area of the DAC are also reduced by 40% as a result. In
addition,