A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR

Abstract

This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase of power, several SNR and SFD R enhancement techniques are proposed. Firstly, the ADC repeats comparison of LSB by using re- dundant DAC to average comparator noise and improve SNR. The technique also corrects settling e rror adaptively, which extends operation speed to 50 MHz even t hough extra comparison period is added for averaging. Secondly, simple filtering method for reducing DAC noise is introduced to achieve further improvement of SNR. Finally, new dithering method is proposed to enhance SFDR. Injecting noise-shaped, multi-valued and uniform-dis- tributed dither to input of the ADC, spurs caused by capacitance mismatches of DAC can be suppressed more effectively compared with conventional dithering. Th ese techniques can be realized by simple circuits in addition to a basic SAR ADC configuration and do not need high power consu mption. The chip is fabricated i na9 0n mC M O Sp r o c e s sa n do c c u p i e s0 . 1m m 2 including all correction logic. The ADC achieved a peak figure of merit (FoM) of 168.7 dB.