← 返回 JSSC 论文列表JSSC 2015第6期Data Converters65nmTime-Interleaved ADCPLL
A High-Linearity Digital-to-Time Converter Technique Constant-Slope Charging Jia
提出恒定斜率充电法实现高线性度数字时间转换器（DTC）。
65nm CMOS, 10 bit DAC, 19 ps to 189 ps delay, 19 fs to 185 fs resolution, 0.17% INL at 189 ps, 1.8 mW
数字时间转换器恒定斜率充电积分非线性频率域测量低功耗
▸创新点1：恒定斜率充电法提高积分非线性（INL）——采用恒定斜率充电技术替代传统可变斜率方法，显著改善了DTC的积分非线性（INL），实测INL低至0.17%（189 ps满量程）和0.34%（19 ps满量程），实现了8-9位有效分辨率（电路创新）
▸创新点2：频率域方法测量高分辨率时间延迟——开发了一种基于频率域的测量技术，通过调制DTC边缘并分析杂散强度来推导INL，解决了传统示波器无法可靠测量飞秒级时间分辨率的问题（方法创新）
▸创新点3：低功耗设计——在65nm CMOS工艺下实现了仅1.8mW的功耗，同时保持210fs以下的输出RMS抖动，展现了优异的能效比（电路创新）
▸创新点4：可编程全量程延迟范围——支持19ps至189ps的可编程全量程延迟，分辨率达到19fs至185fs，提供了灵活的时间延迟控制能力（系统创新）
Abstract
A digital-to-time converter (DTC) controls time delay
by a digital code, which is useful, for example, in a sampling oscillo-
scope, fractional-N PLL, or time-interleaved ADC. This paper pro-
poses constant-slope charging as a method to realize a DTC with in-
trinsically better integral non-linearity (INL) compared to the pop-
ular variable-slope method. The proposed DTC chip realized in 65
nm CMOS consists of a voltage-controlled variable-delay element
(DTC-core) driven by a 10 bit digital-to-a