A Noise-Cancelling Receiver Resilient t oL a r g eH a r m o n i cB l o c k e r s

Abstract

By employing two passive-mixer-based downconver- sion paths, a recently proposed noise cancelling receiver achieves a low-noise figure and tolerates most out-of-band blockers up to 0 dBm with little performance de gradation. However, like most wideband passive-mixer-based designs, the architecture is far less tolerant of harmonic blockers, that is blockers located at or around precise integer multiples of the LO frequency . These blockers are problematic because they are d ownconverted inside the band- width of the baseband TIAs and, so, experience significant on-chip voltage gain. This work presents an enhanced noise-cancelling architecture that prevents harmonic blockers experiencing large on-chip gain, thereby boosting th e receiver's resilience to such blockers. It will be shown that separate techniques are required for the voltage-driven main path and the current-driven auxiliary path. To validated these ideas, single-ended and fully-differential prototypes were fabricated in 28 nm silicon.