JSSC 2015第6期Data Converters90nmPipeline ADC

An Ultra-Low-V oltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Ampliﬁers

本文介绍了一种0.55V、7位、160MS/s的流水线ADC，采用动态放大器和插值架构提升性能。

90nm CMOS, 0.55V, 160MS/s, 2.43mW, ENOB 6.0 bits

超低电压动态放大器流水线ADC插值架构时钟可调功耗

▸创新点1：采用高速开环动态放大器结合共模检测技术（电路创新），显著提升ADC速度至160 MS/s，同时增强对电源电压缩放的鲁棒性，解决了传统闭环放大器在超低电压下的速度限制问题。

▸创新点2：提出插值流水线架构（系统创新），将传统流水线ADC对绝对增益精度的要求转化为相对增益精度，有效降低动态放大器的增益误差影响，实现7位精度下仅需0.55V供电。

▸创新点3：动态放大器实现时钟可调功耗机制（方法创新），通过动态调整时钟频率和放大器偏置，使功耗随采样率线性变化，最终在160 MS/s时功耗仅2.43 mW，FoM达240 fJ/step。

▸创新点4：在90 nm CMOS工艺中实现0.55V超低电压工作（工艺创新），通过共模检测技术和动态放大器非线性分析，克服深亚微米工艺下低压模拟设计的阈值电压限制，ENOB保持6.0 bits。

Abstract

This paper presents a 0.55 V , 7 bit, 160 MS/s pipeline ADC using dynamic ampliﬁers. In this ADC, high-speed open-loop dynamic ampliﬁers with a common-mode detection technique a re used as residue ampliﬁers to increase the ADC's speed, to enhance the robustness against supply volt age scaling, and to realize clock- scalable power consumpti on. To mitigate the absolu te gain con- straint of the residue ampliﬁers in a pipeline ADC, the interpo- lated pipeline architecture is employed to shift the gain require- ment from absolute to relative accuracy. To show the new require- ments of the residue ampliﬁers, the effects of gain mismatch and nonlinearity of the dynamic ampliﬁers are analyzed. The 7 bit pro- totype ADC fabricated in 90 nm CMOS demons trates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM o f the ADC is 240 fJ/con- version-step.