Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-V oltage Synchronous Switching Power Converters Zhidong Liu , Student Member , IEEE

Abstract

Two integrated high-speed gate drivers to enable high-frequency operation of synchr onous rectifiers in high-voltage switching power converters are presented in this paper. The first synchronous gate driver for a CMOS power train consists of a capacitively coupled level shi fter (CCLS) that offers negligible propagation delays and no static current consumption, and requires only one off-chip capac itor to enable high-side power pMOS driving capability without any external floating supply. The second synchronous gate driver consists of a low-power high-speed dynamically controlled level shifter (DCLS) with a reliability-en- hanced error-suppression tech nique for driving a dual-nMOS power train. In addition, a dynamic timing control (DTC) is developed to generate proper dead time for power FETs in order to enable soft switching operati on of the converter under different input voltages for enhancing the converter reliability. The con- verter power efficiency can be also improved by minimizing both switching and short-circuit power losses under high-input-voltage conditions. Implemented in a 0.5 µm 120 V CMOS process, both proposed CCLS and DCLS have demonstrated to shift up 5 V signal to 100 V and 40 V , respectively, improving the FoM by at least 10 times and 2.9 times compare d to respective state-of-the-art level shifters. The DTC circuit en ables proper ZVS operation in a synchronous buck converter with the CCLS-based gate driver over a wide input supply range from 40 V to 100