← 返回 JSSC 论文列表JSSC 2015第6期Power Management0.5µm
Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and
设计高效高速电平转换的片上栅极驱动器，用于高压开关电源转换器。
0.5µm 120V CMOS, 5V信号转换至100V/40V, FoM提升10倍/2.9倍
栅极驱动器电平转换同步整流器软开关高压CMOS
▸电容耦合电平转换器（CCLS）实现无静态功耗和极小传播延迟
▸动态控制电平转换器（DCLS）结合错误抑制技术提升可靠性
▸动态时序控制（DTC）优化死区时间实现软开关操作
Abstract
Two integrated high-speed gate drivers to enable
high-frequency operation of synchr onous rectifiers in high-voltage
switching power converters are presented in this paper. The first
synchronous gate driver for a CMOS power train consists of a
capacitively coupled level shi fter (CCLS) that offers negligible
propagation delays and no static current consumption, and
requires only one off-chip capac itor to enable high-side power
pMOS driving capability without any external floating supply. The
secon