← 返回 JSSC 论文列表JSSC 2015第6期Memory
Layer-Aware Program-and-Read Schemes for 3D Stackable V ertical-Gate BE-SONOS NA
该论文提出了三种电路级技术来解决3D垂直栅极NAND闪存的跨层工艺变异问题。
8层3DVG NAND，200mV跨层失配，编程周期减少25%，SM损失减少56%
3D垂直栅极NAND跨层工艺变异编程验证读取位线预充电存储可靠性
▸分布式NAND串扰消除(DNSS)
▸层感知编程验证读取(LA-PV-R)
▸层感知位线预充电(LA-BP)
Abstract
3D vertical-gate (3DVG) NAND flash is a promising
candidate for next-generation high-density nonvolatile memory.
Cross-layer process variation renders 3DVG NAND susceptible to
decreased speeds, yield, and reliability. This can be attributed to
(a) cross-layer mismatch in bitline capacitance (
), (b) the need
for long program cycles, and (c) s ensing-margin (SM) loss induced
by the effects of background-pattern-dependency (BPD). This
study proposes three circuit-level techniques to overcome these