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A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration
一种采用分离ADC校准技术的12位195MS/s流水线ADC，实现82dB SFDR和53mW功耗。
12bit, 195MS/s, 82dB SFDR, 64.8dB SNDR, 53mW, 1V supply
流水线ADC分离ADC校准增益误差校正失真校正能效优化
▸采用分离ADC校准技术校正增益和失真误差
▸放宽前两级残留放大器建立精度以提高能效
▸在40nm CMOS工艺下实现高动态性能
Abstract
A 12 bit pipeline ADC with residue amplifiers cali- brated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowe red to achieve higher energy ef- ficiency and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical op amp implementation, the settl ing accuracy of the residue am- plifier was relaxed by a factor of more than 3x in the first two stages and by 2x in the remaining stages. The ADC was imple- mented in 40 nm digital CMOS and shows a Schreier figure-of- merit of 157.5 dB at 1 V supply, sampling at 195 MS/s, with an SNDR/SFDR of 64.8 dB/82 dB. While working in continuous back- ground mode, the split-ADC calibration improved the ADC SFDR by 37 dB within 70,000 samples.