An On-Die All-Digital Power Supply Noise Analyzer With Enhanced

Abstract

A scalable all-digital power supply noise analyzer with 20 GHz sampling bandwidth and 1 mV resolution is demonstrated in 32 nm CMOS tec hnology for enabling low-cost low-power in-situ power supply noise measurements without dedicated clean supplies and clock sources. This subsampled averaging-based analyzer meas ures power supply noise in both the equivalent-time and frequency domains with low-resolution VCO-based ADCs. For equivalent-ti me measurements, the accu- rate impedance characterization of power delivery networks is simply done by measuring a clock-synchronized current-step re- sponse. For frequency- domain measurements, the digital random phase-noise accumulation techn ique is analyzed and verified to overcome the clock-and-noise correlation issue in autocorrela- tion measurements. In general large scale integrated circuits and systems, the entire power s upply noise analyzer consumes negligible active and leakage powers because of the MHz-range sampling clock frequency and fully digital implementation with only hundreds of logic gates.