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Area Efficient Integrated Gate Drivers Based on High-V oltage
提出三种全集成自举电路方案,通过高压电荷存储减少面积并提升性能。
电压跌落<1V, 电容75.8pF+18.9pF
自举电路高压电荷存储集成门驱动器面积优化线性稳压器
▸创新点1:采用双电容结构优化自举电路(方法创新)。通过主电容与辅助电容的协同工作,辅助电容预先充电至更高电压,显著提升电荷分配效率,实测电压跌落低于1V,解决了传统单电容面积大且驱动不足的问题。
▸创新点2:集成线性稳压器补偿电压降(电路创新)。在自举电源路径中嵌入线性稳压器,动态补偿二极管压降,确保NMOS栅极过驱动电压稳定,提升驱动可靠性,同时维持整体集成度。
▸创新点3:高压电荷存储技术减少70%面积(系统创新)。利用高压电荷存储机制,双电容(75.8pF+18.9pF)总面积较传统方案缩减70%,实现高电流驱动器的全集成,适用于SMPS和Class-D等功率级应用。
▸创新点4:提供电容尺寸设计准则(方法创新)。论文提出量化设计规则,指导主辅电容容值比例优化,平衡面积与性能,为同类集成自举电路提供标准化设计依据。
Abstract
For area reasons, NMOS transistors are preferred over PMOS for the pull-up path in gate drivers. Bootstrapping has to ensure sufficient NMOS gate overdrive. Especially in high-cur- rent gate drivers with large transistors, the bootstrap capacitor is too large for integration. This paper proposes three options of fully integrated bootstrap circuits. The key idea is that the main bootstrap capacitor is supporte d by a second bootstrap capacitor, which is charged to a higher voltage and ensures high charge allocation when the driver turns on. A capacitor sizing guideline and the overall driver implementa tion including a suitable charge pump for permanent driver activation is provided. A linear regulator is used for bootstrap supply and it also compensates the voltage drop of the bootstrap diode. Measurements from a testchip in 180 nm high-voltage BiCMOS confirm the benefit of high-voltage charge storing. The f ully integrated bootstrap circuit with two stacked 75.8 pF and 18.9 pF capacitors results in an expected voltage dip of lower than 1 V. Both bootstrap capacitors require 70% less area compared to a conventional bootstrap cir- cuit. Besides drivers, the proposed bootstrap can also be directly applied to power stages to achieve fully integrated switched mode power supplies or class-D output stages.