Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

Abstract

This paper describes the clock distribution and syn- chronization network for a 64 bit ARMv8 8-core microprocessor . Embedded in a SoC for cloud com puting platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter 1p s a n d f e a t u res dynamic frequency hopping for DVFS applications. In conjunc- tion with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves 0.8 ps/mV rms and 9 ps of period jitter and skew, re- spectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and e ase timing crit- ical paths, the processor perfor mance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excu rsions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high sp eed synchronization oper- ations, is proposed.