A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

Abstract

This paper describes a 0.5–16.3 Gb/s fully adaptive w i r e l i n et r a n s c e i v e re m b e d d e di n2 0n mC M O SF P G A .T h e receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still pro- viding flexibility to support mult iple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wid e range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrat ure-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER 10 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes.