← 返回 JSSC 论文列表JSSC 2015第8期RF & Wireless32nm SOI CMOSEqualizer
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology Timothy O. Dickson , Senior Member , IEEE,Y o n g L i u, Member , IEEE, Sergey V. Rylov , Member , IEEE
一款功率可扩展的14 pJbit 1612 Gbs源同步IO，采用DFE接收器，32nm SOI CMOS工艺。
12 Gb/s每通道，1.4 pJ/b效率（0.75英寸Megtron-6 PCB），1.9 pJ/b效率（20英寸Megtron-6 PCB）
源同步IODFE接收器功率可扩展低功耗高速传输
▸创新点1：可控TX驱动振幅（电路创新）。通过动态调整发射端驱动器的输出振幅，优化功耗与信号完整性，支持低损耗和高损耗通道，实现1.4 pJ/b至1.9 pJ/b的能效提升。
▸创新点2：灵活的RX均衡（电路创新）。接收端采用可配置均衡器，适应不同信道损耗条件，确保12 Gb/s速率下的信号质量，支持从0.75"到20" PCB传输的稳定性能。
▸创新点3：多模式去歪斜技术（系统创新）。提供多种时钟去歪斜模式，减少信号传输中的时序偏差，提升系统同步精度，适用于低歪斜和高歪斜的互连场景。
▸创新点4：低歪斜传输线时钟分布（电路创新）。采用优化的时钟分布网络，显著降低时钟信号歪斜，确保高速数据传输的时序一致性，支持12 Gb/s的稳定运行。
Abstract
A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source- synchronous I/O includes con- trollable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-los s channels without loss of band- width. Transceiver circuit inn ovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SO I CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces.