An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation Saman Saeedi, Student Member , IEEE

Abstract

This paper presents a low-power first-order fre- quency synthesizer architecture suitable for high-speed on- chip clock generation. The proposed de sign features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digita l coarse-tuning and rotational frequency detection for fine-tuning. Similar to mul- tiplying delay-locked loops (MDLLs ), this architecture limits jitter accumulation to one reference cycle, as jitter du ring one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase inter polation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8–9.5 GHz, LC VCO's range of operation. First-order dynamic of th e acquisition has been analyzed and demonstrated thr ough measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rm s jitter of 680 fs. Different components of jitter have been an alyzed and separate measure- ments have been done to support the analysis. The reference spurs are measured to be 64.3 dB below the carrier frequency. At 8G H zt h es y s t e mc o n s u m e s2 . 4 9m Wf r o ma1Vs u p p l y .