← 返回 JSSC 论文列表JSSC 2015第8期Clocking & PLLsVCOClock Generation
An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generatio
提出一种低功耗一阶频率合成器架构，适用于高速片上时钟生成，工作频率8-9.5 GHz。
8 GHz输出时钟，集成rms抖动490 fs，峰峰值周期抖动2.06 ps，总rms抖动680 fs，参考杂散-64.3 dBc，功耗2.49 mW@1V
频率合成器低功耗LC VCO相位插值时钟生成
▸采用LC正交压控振荡器(VCO)与采样保持电路结合
▸通过相位插值实现参考时钟边沿注入
▸数字粗调与旋转频率检测的精细调谐
Abstract
This paper presents a low-power first-order fre-
quency synthesizer architecture suitable for high-speed on- chip
clock generation. The proposed de sign features an architecture
combining an LC quadrature voltage-controlled oscillator (VCO),
two sample-and-holds, a phase interpolator, digita l coarse-tuning
and rotational frequency detection for fine-tuning. Similar to mul-
tiplying delay-locked loops (MDLLs ), this architecture limits jitter
accumulation to one reference cycle, as jitter du ring