Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS

Abstract

It is traditionally challenging to implement higher- order PWM closed-loop Class-D audio amplifiers using analog in- tensive techniques in deep-submicron, low voltage process tech- nologies. This is primarily attributed to reduced power supply, de- graded analog transistor characte ristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed -loop mixed-signal architecture incorporating digital control and integrate a fourth-order ampli- fier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, si- multaneously accomplishing i mprovements in THD+N and PSRR. The overall architecture is inhere ntly amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.