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A0 . 0 2m m 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
一种基于65nm CMOS工艺的超紧凑开关电容低通滤波器,具有0.5至10 MHz带宽可调性。
65nm CMOS, 0.02mm² die size, 0.5-10MHz带宽可调, 59.2dB SFDR, +17.6dBm IIP3, 19.5nV/√Hz输入噪声
开关电容滤波器低通滤波器CMOS带宽可调高线性度
▸采用无内部增益的被动开关电容网络和开环单位增益缓冲器,更适合技术微缩
▸在单个时钟周期内递归实现具有独立Q因子的复极点对,同时确保低串扰
▸通过1x循环利用SC缓冲器Biquad结构实现75%缓冲器利用率
Abstract
This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-c ompact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-l oop unity-gain buffers; both are friendlier to technology downscaling than most c onventional Biquads that use high-gain amp lifiers and closed-loop negative feedback. Complex-pole pairs with independent Q factors are re- cursively realized in one clock period, wh ile ensuring low crosstalk effect between the formations of each pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-r ecycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occup ies a die size of only 0.02 mm and exhibits 20x bandwidth tunability (0 .5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-o f-merit which are favorably comparable with the recent art. The 1 dB compression point conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end g ain.