A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS Viki Szortyka Qixian

Abstract

A6 0G H zs u b - s a m p l i n gP L Li m p l e m e n t e di n4 0n m CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an induc tively-peaked static divide- by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8–63.3 GHz QVCO uses super-harmonic coupling a t 120 GHz