← 返回 JSSC 论文列表JSSC 2015第9期Other90nm SiGe-BiCMOS
A DC-100 GHz Active Frequency Doubler With a Low-V oltage
90nm SiGe-BiCMOS工艺下实现DC-100 GHz宽带有源倍频器，采用非对称偏置核心结构
12dB@10GHz转换增益，0dB@100GHz，25dBc@12.5GHz杂散抑制，55.5mA@4.5V
有源倍频器毫米波SiGe-BiCMOS谐波抑制宽带电路
▸电路创新：采用交叉耦合差分对实现偶次有源倍频，显著提高了频率倍增效率，尤其在低频段（如10 GHz）实现12 dB的转换增益。
▸方法创新：通过非对称偏置技术构建偶次传递函数，有效抑制奇次谐波，显著降低杂散信号（如12.5 GHz输入音调杂散为-25 dBc）。
▸系统创新：集成宽带和窄带倍频器，并通过仿真对比其性能，验证了宽带倍频器在0-100 GHz范围内的频率响应和转换增益特性。
▸电路创新：设计包含反馈调节偏置的有源负载和50Ω输入输出缓冲器的宽带倍频器原型，实测验证了电路概念，芯片面积仅0.37 mm²，功耗为55.5 mA@4.5 V。
Abstract
Cross-coupled differential pairs implement an even-order active frequency multiplier in 90 nm SiGe-BiCMOS. The multiplier core uses asymmetric biasing to realize an even-order transfer function . Wideband (WB) and narrowband doublers built around the activ e core are proposed, and their relative performance is compare d from simulation. Measurement of a WB prototype consisting of the doubler, active load with feedback regulation of bias, and 50 input and output buffers validates the circuit concepts. C onversion gain (CG) for the WB doubler peaks at low frequency (e.g., 12 dB at 10 GHz) and rolls off to 0 dB at 100 GHz. For 25 GHz output, significant spurs are: 25 dBc at 12.5 GHz (input tone) and 28 dBc at 50 GHz (4th harmonic). The 0.37 mm WB testchip consumes 55.5 mA from a 4.5 V supply.