A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS Chih-Wei Chen, Student Member , IEEE

Abstract

The dual-frequency single-inductor multiple-output (DF-SIMO) buck converter to pology is proposed. Unli ke conven- tional single-frequency SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency ( 2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V , while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and o utput stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A low-power 5-ou tput 2 MHz/120 MHz design in 45 nm with 1.8 V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 V to 1.6 V , with 4 outputs providing up to 15 m A and one output providing up to 50 mA. The design uses single 10 µH off-chip inductor, 2 nF on-chip capacitor for each 15 mA output and 4.5 nF for the 50 mA output. The peak efficiency is 7 3%, dynamic voltage scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/u ndershoot or cross-regulation transients.