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A Reference-Less Single-Loop Half-Rate Binary CDR Mohammad Sadegh Jalali Studen
提出一种无参考单环路半速率二进制CDR，工作范围8.5-12.1 Gb/s，捕获范围提升36%。
8.5-12.1 Gb/s, 11 mW, 65nm CMOS
无参考单环路半速率二进制CDR频率检测
▸新型频率检测机制限制输入数据与VCO时钟的相位误差
▸生成数据的三个相位并选择最小化CDR相位误差的相位
▸在65nm CMOS中实现10 Gb/s CDR，功耗11 mW
Abstract
This paper proposes a half-rate single-loop reference-
less binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% cap-
ture range). The high capture range is made possible by adding a
novel frequency detection mecha nism which limits the magnitude
of the phase error between the input data and the VCO clock. The
proposed frequency detector pro duces three phases of the data,
and feeds into the phase detector the data phase that minimizes the
CDR phase error. This frequency detector, implemente