An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

Abstract

An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 mC M O Si sp r e s e n t e d .B yr e a l izing an asymmetric phase detector transfer curve, the linear CDR's “single-sided” capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the ne ed for the reference clock and the separate frequency detector in conven- tional dual-loop CDRs. Robust f requency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitte r tolerance performance. The measurement results show that with a 10.3 Gb/s 2 -1 PRBS input, the random jitter at the output data is 0.336 ps , and the out-of- band jitter tolerance is 0.34 UI - .