JSSC 2015第9期Data Converters65nmVCO

Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC

通过滤波抖动技术实现50MHz带宽10位ENOB的VCO基ADC线性化

65nm CMOS, 10 ENOB, 50 MHz带宽, 82 mW, 90 fJ/conv.step

VCO基ADC滤波抖动线性化MASH结构高分辨率

▸创新点1：滤波抖动技术消除VCO非线性（方法创新）。通过引入滤波抖动技术，有效抑制了VCO非线性特性带来的动态范围限制，将非线性误差转化为白噪声，显著提升了ADC的线性度和动态范围。该技术无需复杂的校准或反馈环路，降低了功耗（82 mW）和设计复杂度。

▸创新点2：0-1 MASH结构处理残余信号（系统架构创新）。采用两级结构（粗调+精调），其中VCO-ADC作为精调级处理粗调级的残余信号，结合MASH架构的优势，实现了高分辨率（10-bit ENOB）和宽带宽（50 MHz）的同步优化。

▸创新点3：高分辨率宽带原型设计（电路实现创新）。在65 nm CMOS工艺下实现，通过优化信号处理链（如滤波、抖动注入等），在50 MHz带宽内达到90 fJ/conv.step的优值系数（FoM），兼顾了低功耗（8.2 mW）与高性能。

▸创新点4：混合信号处理技术（方法创新）。结合模拟域抖动注入与数字域滤波，有效分离非线性谐波成分，避免了传统校准算法的计算开销，为VCO-ADC的实用化提供了新思路。

Abstract

Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range of analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance the dynamic range include em- bedding the VCO-based ADC in a loop or to post-process the digital data for calibration, both of which impose signiﬁcant power constraints. In contrast, in this work the VCO-based ADC is linearized through a ﬁltered dithering technique, wherein the VCO-based ADC is used as a ﬁne stage that processes the residue from a coarse stage in a 0–1 MASH structure. The proposed ﬁltered dithering technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO non linearity. The work resorts to multiple other signal processing t echniques to build a high-resolu- tion, wideband prototype, in 65 nm complementary metal-oxide semiconductor (CMOS), that achi eves 10 effective number of bits (ENOB) in digitizing signals with 50 MHz bandwidth consuming 8.2 mW at a ﬁgure of merit (FoM) of 90 fJ/conv.step.