JSSC 2015第9期Other40nm

SEPTEMBER 2015 VOLUME 50 NUM BER 9 IJSCBC ISSN 0018-9200 REGULAR PAPERS A DC-100

本文介绍了多种CMOS技术下的高性能电路设计，包括功率放大器、滤波器、ADC和PLL等。

DC-100 MHz, 59.2 dB SFDR, 60 dB SNDR, 35 MS/s, 200 fs抖动

CMOS功率放大器滤波器ADCPLL

▸双模CMOS Doherty功率放大器

▸可扩展带宽的SC LPF

▸基于比较器噪声的随机残差估计

Abstract

L on g 1963 Du a l - Mo de CMO S Do h e r t y L TE Po we r A mp l if i e r W it h Sy mm e tr ic Hy b r i d T r a n s f or me r ................................... ................................................................................................... E . K a y ma k s u t a nd P . R e y n a e rt 1974 A0 . 0 2m m 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz B andwidth Scalability Exploiting a Recycling SC - Bu f f e r B iq u a d ........................... ........................