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JSSC 2015第10期Data ConvertersDelta-Sigma ADC

A0 . 4V6 3 W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator Y ounghyun Y oon

提出一种0.4V低电压Δ-Σ调制器,采用混合开关积分器,无需时钟提升或自举开关。
0.4V, 63µW, 76.1dB SNDR, 20kHz带宽
Δ-Σ调制器低电压混合开关积分器失真抑制低功耗
创新点1:混合开关积分器设计(电路创新)。该论文提出了一种结合开关电阻和开关电容操作的混合开关积分器,有效降低了在0.4V低电源电压下的失真,通过将开关置于放大器的虚拟地节点,避免了导通电阻变化带来的失真问题。
创新点2:无时钟提升的低电压设计(系统创新)。该设计在不依赖时钟提升或自举开关的情况下实现了0.4V超低电源电压工作,避免了传统设计中需要内部高压生成电路的复杂性,同时保持了76.1 dB的SNDR和82 dB的动态范围。
创新点3:高鲁棒性性能(系统创新)。该调制器在±10%的电源电压变化和宽温度范围内表现出稳定的性能,实测总功耗仅为63 µW,展示了其在恶劣环境下的可靠性和实用性。
创新点4:虚拟地节点开关布局(电路创新)。通过将开关放置在放大器的虚拟地节点,显著减少了导通电阻变化对系统线性度的影响,从而在低电压下实现了高精度(20 kHz带宽内SNDR达76.1 dB)。
Abstract
This paper presents a delta-sigma modulator op- erating at a supply voltage of 0.4 V. The designed delta-sigma modulator uses a proposed hybrid switching integrator and operates at a low supply voltage wi thout clock boosting or boot- strapped switches. The propos ed integrator consists of both switched-resistor and switched-c apacitor operations and signif- icantly reduces distortion at a l ow supply voltage. V ariation in the turn-on resistance, which is the main source of distortion, is avoided by placing the switches at the virtual ground node of the amplifier. The proposed low-vol tage design scheme can replace commonly-used clock boosting techniques, which rely on internal high-voltage generation circuits. A fabricated modulator achieves a 76.1 dB signal-to-noise-plus-distortion ratio (SNDR) and an 82 dB dynamic range at a 20 kHz bandwidth. The measured total power consumption is 63 µW from a 0.4 V supply voltage. The measured results show robust S NDR performance, even at ±10% supply voltage variations. The mea sured results also show stable performance over a wide temperature range.