A Refresh-Less eDRAM Macro With Embedded V oltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder Woong Choi, Student Member , IEEE , Gyuseong Kang , Student Member , IEEE ,a n d

Abstract

This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder , refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single- supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference volt age generation scheme to support single-ended read operation. Thanks to the decoupled rea da n d write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To fur ther reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and com- putational logics is identified and eliminated witho ut latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip mea surement results sho w 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.