JSSC 2015第10期Memory65nmDRAM

A Refresh-Less eDRAM Macro With Embedded V oltage Reference and Selective Read f

提出一种基于2T增益单元的无刷新eDRAM设计，用于IEEE 802.11n WLAN的Viterbi解码器。

65nm CMOS工艺，24 kb eDRAM，面积节省44%，功耗节省39%

eDRAMViterbi解码器无刷新单电源电压双端口操作

▸创新点1：无刷新操作设计（方法创新）。通过确保幸存内存的读写周期短于增益单元的保持时间，完全消除了eDRAM的刷新操作，显著降低了功耗并提高了系统效率。

▸创新点2：单电源电压写入技术（电路创新）。提出了一种有益的读字线（RWL）耦合技术，简化了写入操作，仅需单一电源电压，降低了电路复杂度和功耗。

▸创新点3：双端口操作支持（系统创新）。利用增益单元的读写分离结构，实现了双端口操作，无需额外面积开销，使内存带宽翻倍，提升了Viterbi解码器的性能。

▸创新点4：嵌入式电压参考生成方案（电路创新）。提出了一种参考电压生成方案，支持单端读取操作，进一步优化了读取性能并降低了功耗。

Abstract

This paper presents a Viterbi-speciﬁc 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder , refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single- supply voltage, a beneﬁcial read word-line (RWL) coupling technique is proposed. In this work, we also present a re