▸创新点1：采用混合2 IIR和1离散抽头DFE结构，显著降低功耗至0.41 pJ/bit，实现了10 Gb/s高速数据传输（系统创新）
▸创新点2：优化IIR滤波器设计，有效抑制码间干扰（ISI），提升信号完整性（电路创新）
▸创新点3：在28 nm-LP CMOS工艺下实现高性能DFE，展示了先进工艺下的低功耗高速电路设计潜力（工艺创新）
▸创新点4：通过创新的DFE架构，在保持高性能的同时简化了电路复杂度，降低了制造成本（方法创新）
Abstract
an Shahramian and Anthony Chan Carusone
In the above paper [1], a mistake was made during printing and
Fig. 9(b) was overwritten with Fig. 9(a). The correct Fig. 9 is shown
below.
In addition, Equation (4) should read:
(4)
IEEE regrets the errors.
Manuscript received August 19, 2 015; accepted August 19, 2015. Date of
publication September 07, 2015; date of current version September 24, 201 5.
The authors are with the Department of Electrical and Computer Engi-
neering, University of Toronto, To