A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

Abstract

This paper presents a low- cost successive approx- imation register (SAR) analog-to-digital converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled re- combination capacitor weighting method is disclosed. The digital sub-blocks in this ADC are composed of standard library logic cells. The prototype is fabrica ted in a 1P8M 20 nm CMOS tech- nology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68 mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and Nyquist input frequency, respectively, resulting in figures of merit (FoMs) of 6.8 and 7.3 fJ/conversion-step, respectively. At 1 V supply and 320 MS/s, the ADC consumes 1.52 mW. It achieves an SNDR of 57.1 dB and 50.89 dB at low and Nyquist input frequency, respectively, resul ting in FoMs of 8.1 and 16.5 fJ/con- version-step, respectively. Th e ADC core only occupies an active area of m m.