JSSC 2015第11期Data Converters20 nmSAR ADC

A 10 bit 320 MSs Low-Cost SAR ADC for IEEE 80211ac Applications in 20 nm CMOS Ch

一款用于IEEE 802.11ac应用的低成本SAR ADC，采用20 nm CMOS工艺，具有高能效和小面积。

20 nm CMOS, 0.9 V/1 V, 160 MS/s/320 MS/s

SAR ADCIEEE 802.11ac低功耗20 nm CMOS二进制缩放重组电容

▸二进制缩放重组电容加权方法

▸数字子模块采用标准库逻辑单元

▸在20 nm CMOS工艺中实现高能效和小面积

Abstract

This paper presents a low- cost successive approx- imation register (SAR) analog-to-digital converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled re- combination capacitor weighting method is disclosed. The digital sub-blocks in this ADC are composed of standard library logic cells. The prototype is fabrica ted in a 1P8M 20 nm CMOS tech- nology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68 mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and Nyquist input f