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A 168 GbpsChannel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Inte
提出一种65nm CMOS工艺的16.8 Gbps单端收发器，用于SiP基DRAM接口。
65 nm CMOS, 16.8 Gbps, BER < 1e-12, 5.9 pJ/bit
单端收发器SiPDRAM接口CMOS均衡器
▸创新点1：电流模式4:1 MUX与1-tap FFE结合，通过采用25%占空比时钟防止两相时钟重叠时的短路电流，显著提高了信号完整性和传输效率。
▸创新点2：源极跟随器连续时间线性均衡器，有效应对Si载体通道中的共模变化，提升了单端信号传输的质量和稳定性。
▸创新点3：自生成训练算法，通过动态调整接收器参数，优化信号均衡，实现了低于1e-12的误码率（BER），显著提升了系统可靠性。
▸创新点4：采用网状层作为参考的Si载体通道设计，减少了插入损耗，进一步提升了信号传输性能和能效，达到5.9 pJ/bit的能效比。
Abstract
A 16.8 Gbps/channel single-ended transceiver for
SiP-based DRAM interface on silicon carrier channel is proposed
in this paper. A transmitter, receiver , and channel are all included
in a single package as SiP. A current mode 4:1 MUX with 1-tap
feed-forward equalizer (FFE) i s used as a serializer, and this
4:1 MUX uses 25% duty clock to prevent short circuit current
when consecutive 2-phase clocks overlap. Additionally, an open
drain output driver with asynchronous type 1-tap FFE is used in
the