A 17 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked

Abstract

Although multiplying delay-locked loops allow clock frequency multiplication with ver y low phase noise and jitter, their application has been so far limited to integer- N multiplication, and the achieved reference-spur perf ormance has been typically lim- ited by time offsets. This paper presents the first published multi- plying delay-locked loop achieving fine fractional- N frequency res- olution, and introduces an automatic cancellation of the phase de- tector offset. Both capabilities are ena