A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

Abstract

Although multiplying delay-locked loops allow clock frequency multiplication with ver y low phase noise and jitter, their application has been so far limited to integer- N multiplication, and the achieved reference-spur perf ormance has been typically lim- ited by time offsets. This paper presents the first published multi- plying delay-locked loop achieving fine fractional- N frequency res- olution, and introduces an automatic cancellation of the phase de- tector offset. Both capabilities are enabled by insertion of a dig- ital-to-time converter in the reference path. The proposed synthe- sizer, implemented in a standard 65 nm CMOS process, occupies ac o r ea r e ao f0 . 0 9m m , and generates a frequency ranging be- tween 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional- N mode, the inte- grated RMS jitter, including random and deterministic compo- nents, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of 232 dB. In integer- N mode, the c i r c u i ta c h i e v e sR M Sj i t t e ro f0 . 4 7p sa t2 . 4m Wp o w e ra n dfi g u r e of merit of 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from 32 to 55 dBc.