A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process Sang-Hyeok Chu, Student Member , IEEE ,W o o r h a m B a e, Student Member , IEEE , Gyu-Seob Jeong, Student Member , IEEE, Sungchun Jang, Sungwoo Kim , Student Member , IEEE, Jiho Joo

Abstract

This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang- bang clock and data recovery circuit. The optical front-end a chieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth exte nsion techniques. In addition, in order to minimize additional j itter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 ps and the measured jitter tolera nce exceeds the tolerance mask specified in IEEE 802.3ba. Th e receiver sensitivity is 106 and 184 A for a bit error rate of at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front -end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.