JSSC 2015第11期RF & Wireless40 nmPLLCDR

A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery Zheng-Hao Hong, Y ao-Chia Liu , Student Member , IEEE

一款19-27 Gbps接收器，采用连续时间线性均衡器和2抽头判决反馈均衡器嵌入时钟数据恢复电路，实现高效能和小尺寸。

40 nm CMOS, 3.12 pJ/bit, 27 Gbps

接收器时钟数据恢复判决反馈均衡器自适应均衡CMOS

▸创新点1：混合CDR以半速率运行，通过将时钟和数据恢复电路嵌入到2-tap DFE中，显著提高了系统的时序恢复能力和抗干扰性能，同时降低了功耗和复杂度。

▸创新点2：自动阈值跟踪电路结合LMS自适应引擎，实现了对不同信道响应的自适应补偿，提高了系统的鲁棒性和灵活性，特别是在高频段（19–27 Gbps）的表现。

▸创新点3：无电感正交松弛型振荡器，通过创新的电路设计避免了传统电感的使用，不仅减小了芯片面积（核心面积仅0.09 mm²），还实现了宽范围操作（19–27 Gbps）和低功耗（3.12 pJ/bit）。

▸创新点4：整体系统的高能效设计，在27 Gbps操作下实现了3.12 pJ/bit的能效，同时补偿了20 dB的信道损耗，展现了在高速数据传输中的卓越性能。

Abstract

A 19–27 Gbps receiver comprised of a continuous- time linear equalizer (CTLE) followed by a 2-tap decision feed- back equalizer embedded clock and data recovery circuit is imple- mented. The hybrid CDR is operated at half rate, which is incorpo- rated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To acco mmodate different channel re- sponse, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the ad- vantages of small form factor and wide range operation (19–27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an en- ergy efﬁciency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm only.