A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process Kristian N. Madsen , Member , IEEE, Timothy D. Gathman , Member , IEEE

Abstract

A high-speed, track-and-hold amplifier and inter- l e a v e dC M O Ss a m p l e - a n d - h o l dc i r c u i ta r ei m p l e m e n t e di na n InP-on-CMOS fabrication process. Conventional 50- interchip interconnects between III-V and CMOS circuits are elimi nated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits a t lower power consumption. The track-and-hold amplifier is based on a double-switchi ng feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, t h i si st h efi r s tp u b l i s h e dr e s u l to fah i g h - s p eed track-and-hold amplifier in an InP BiCMOS process and the first implementa- tion of a feedback linearized tra ck-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buff er with feedback is demonstrated to offer high linea rity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than 53 dBc at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.