Low Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time V ariations

Abstract

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- , and slow read access time ( ) caused by a high cell-re- sistance and small cell-resista nce-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current ( ) resulting from the wide dis- tribution of write (SET)-times ( ). This study proposes a swing-sample-and-couple (SS C) voltage-mode sense ampli- fier (VSA) to enable an approximately greater sensing margin for lower and a faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-terminatio n (SBWT) scheme is proposed to cut off the of devices with a rapid .T h eS B W T scheme reduces 99 of the with an area penalty b e l o w0 . 5 % .Af a b r i c a t e d5 1 2r o w2 8n m1M bR e R A Mm a c r o achieved 404 ns when 0.27 V and confirmed the cutoff by the SBWT.