JSSC 2015第12期Data Converters40 nmSAR ADCNeural Network Accelerator

A 14 b 35 MSs SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Inp

一款14位35MS/s SAR ADC，通过环路嵌入式输入缓冲器实现74.5 dB SNDR和99 dB SFDR。

14位, 35MS/s, 74.5 dB SNDR, 99 dB SFDR, 54.5 mW

SAR ADC输入缓冲器自校准电流导向DAC高精度

▸创新点1：环路嵌入式输入缓冲器（电路创新）。该缓冲器将大采样电容与输入隔离，显著降低了ADC的驱动要求，同时通过SAR操作消除其非线性，仅增加12.5 mW功耗。

▸创新点2：自校准电流导向DAC（系统创新）。内置自校准功能，消除了对外部低阻抗参考的需求，提高了系统的集成度和稳定性，同时简化了设计。

▸创新点3：SAR操作消除缓冲器非线性（方法创新）。通过SAR算法的特性，有效抵消了输入缓冲器的非线性，使得可以使用简单的源跟随器，降低了设计复杂度。

▸创新点4：高性能指标（系统创新）。在40 nm CMOS工艺下，实现了74.5 dB的峰值SNDR和90/99 dB的SFDR，功耗仅为54.5 mW，Schreier FOM达到159.5 dB，展现了优异的性能。

Abstract

This paper presents a 14 bit 35 MS/s successive ap- proximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sam- pling capacitor from the input and thereby eases the ADC drive requirements signiﬁcantly. Since the buffer's nonlinearity is can- celled by the SAR operation, a pair of basic source followers ca