JSSC 2015第12期Data Converters65nmPipeline ADC

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Ampliﬁer Based SAR-Assisted Pipeline ADC

本文提出了一种基于65nm CMOS工艺的13位50MS/s全差分环形放大器SAR辅助流水线ADC，具有高增益和低功耗特点。

65nm CMOS, 1mW, 50MS/s, 70.9dB SNDR

环形放大器SAR ADC开关电容无校准低功耗

▸创新点1：新型全差分环形放大器设计，解决了单端环形放大器的共模噪声和匹配问题，同时保持高增益（>60 dB）、快速压摆率充电和接近轨到轨的输出摆幅，显著提升了放大器的线性度和噪声性能。

▸创新点2：采用开关电容（SC）级间残留放大器结构，结合新型全差分环形放大器实现无校准精确放大，在50 MS/s采样率下达到13位线性度，解决了传统放大器需要校准的复杂性问题。

▸创新点3：提出浮动检测跳过（FDAS）电容DAC切换方法，通过动态跳过冗余切换步骤降低功耗，同时优化第一级CDAC的线性度，使整体ADC的SNDR提升至70.9 dB（11.5位有效精度）。

▸创新点4：系统级整合创新，通过环形放大器与SAR辅助流水线架构的协同设计，在65 nm CMOS工艺下实现1 mW超低功耗（Walden FoM 6.9 fJ/转换步），同时兼顾84.6 dB的SFDR高频性能。

Abstract

This paper presents a 13 bit 50 MS/s fully differen- tial ring ampliﬁer based SAR-assi sted pipeline ADC, implemented in 65 nm CMOS. We introduce a new fully differential ring ampli- ﬁer, which solves the problems of single-ended ring ampliﬁers while maintaining the beneﬁts of high gain, fast slew based charging and an almost rail-to-rail output swing. We implement a switched-ca- pacitor (SC) inter-stage residue ampliﬁer that uses this new fully differential ring ampliﬁer to giv e accurate ampliﬁcation without calibration. In addition, a new ﬂ oated detect-and-skip (FDAS) ca- pacitive DAC (CDAC) switching method reduces the switching en- ergy and improves linearity of ﬁr st-stage CDAC. With these tech- niques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity without calibration and consumes 1 mW. This measured perfor- mance is equivalent to Walden and Schreier FoMs of 6.9 fJ/con- version step and 174.9 dB, respectively.