A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

Abstract

This paper presents a power- and area-efficient multistandard serial link trans ceiver designed for backplane ap- plication rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a contin- uous-time linear equalizer, varia ble gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL em- ploys a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1Vs u p p l yw i t ht r a n s m i t t e rd r i v e ra t1 . 2 5V .S u c hl o wp o w e r consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.