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JSSC 2015第12期Data Converters65nmCharge PumpPLL

A 35 GHz Digital Fractional- N PLL Frequency Synthesizer Based on Ring Oscillato

65nm CMOS工艺下3.5GHz数字分数分频锁相环,性能媲美模拟PLL。
65nm CMOS, 1V, 15.6mW, 0.34mm², -60dBc最大带内分数杂散, -81dBc最差参考杂散, -93/-126/-151 dBc/Hz@100kHz/1MHz/20MHz相位噪声
数字分数分频锁相环环形振荡器频率-数字转换器相位噪声CMOS
新型二阶频率-数字转换器(使用双模式环形振荡器和数字逻辑替代电荷泵和ADC)
减少因DCO输入接近整数边界时组件失配导致的额外相位噪声的技术
优异的杂散抑制和相位噪声性能
Abstract
A 3.5 GHz digital fractional- N PLL in 65 nm CMOS technology is presented that achieves phase noise and spurious tone performance comparable to those of a high-performance analog PLL. It is enabled by a new second-order frequency-to-digital con- verter that uses a dual-mode ring oscillator and digital logic in- stead of a charge pump and ADC. It also incorporates a new tech- n i q u et or e d u c ee x c e s sp h a s en o i s et h a tw o u l do t h e r w i s eb ec a u s e d by component mismatche