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A 45 mW CT Self-Coupled Modulator With 22 MHz BW and 904 dB SNDR Using Residual
一种采用自耦合技术的低功耗连续时间调制器，实现90.4dB SNDR和2.2MHz带宽。
55nm LP CMOS, 1.2V/1.8V, 4.5mW, 2.2MHz BW, 90.4dB SNDR
连续时间调制器自耦合技术残余信号补偿低功耗设计动态元件匹配
▸连续时间自耦合技术(CTSC)
▸利用残余信号进行环路延迟补偿
▸低纹波DAC锁存器和低切换率DEM算法
Abstract
This paper presents a power-efficient single-loop
continuous-time (CT) modulator (DSM) that achieves a
SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modu-
lator uses a fourth-order feed-forw ard architecture incorporating
the continuous-time self-coupl ing (CTSC) technique. Moreover,
to reduce hardware area, this design utilizes the residual signal
for excess loop delay (ELD) compensation. To improve linearity,
low-ripple DAC latches and low toggle-rate dynamic element
matching (DEM) algor