A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming Y

Abstract

An auto-zero and chopper operational amplifier with a 4.5–60 V supply voltage range is realized, using a 0.18 m CMOS process augmented by 5 V CMOS and 60 V DMOS tran- sistors. It achieves a maximum offset voltage drift of 0.02 V C, a minimum CMRR of 145 dB, a noise PSD of 6.8 nV , and a 3.1 MHz unity gain bandwidth, while dissipating 840 A of current. Up-modulated chopper ripple is suppressed by auto-zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias cu rrent due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.