Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers Ahmed Elkholy, Student Member , IEEE, Mrunmay Talegaonkar, Student Member , IEEE, Tejasvi Anand, Student Member , IEEE, and Pavan

Abstract

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the pro- posed FTL continuously tunes the oscillator’s free-running fre- quency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large- signal analysis for phase domain response (PDR) of injection- locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of frequency error on injection strength and phase noise perfor- mance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25 mm 2. The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of 190 fs rms, while consuming 2.25 mW power . This translates to an excellent figure-of-merit (FoM) of −251 dB, which is the best reported high-frequency clock multiplier .