← 返回 JSSC 论文列表JSSC 2019第1期Power Management28nmPLLTDC
A 00043-mm2 0312-V Frequency-Scalable Synthesized Fractional-N Digital PLL With
一种采用推测双参考插值时间数字转换器的合成小数分频数字锁相环，具有宽频率锁定范围和低功耗。
28nm CMOS, 0.3-1.2V, 0.0043mm², FOM < -220dB (VDD > 0.6V)
小数分频数字锁相环时间数字转换器数字控制振荡器自动综合低功耗
▸推测双参考插值时间数字转换器（DI-TDC）
▸无需校准的一阶增益匹配
▸通过预测感兴趣时间区域最小化DI-TDC的功耗和面积
Abstract
This paper presents a synthesized fractional-N dig-
ital phase-locked loop (PLL) with a speculative dual-referenced
interpolating time-to-digital converter (DI-TDC). The DI-TDC
measures a fractional phase by referencing two adjacent quad-
rant boundaries which are given by a four-phase digitally
controlled oscillator (DCO). It achieves a robust gain matching
to the first order without need of any calibration. By predicting
a time region of interest for the next TDC conversion, the
power and area