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A 00056-mm2 249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Freque
一种采用块共享无偏移频率跟踪环路的超紧凑全数字MDLL，具有低功耗和高性能。
28nm CMOS, 0.8V, 1.55-3.35GHz, 292fs rms jitter, 1.45mW, FoM -249dB
全数字MDLL频率跟踪环路静态相位偏移变容调谐VCO低功耗
▸采用块共享无偏移频率跟踪环路（FTL）校准VCO频率变化
▸使用数字控制延迟线（DCDL）和相邻边沿选择器精确检测静态相位偏移（SPO）
▸变容调谐双复用环形VCO（MRVCO）减少抖动变化并扩展频率调谐范围
Abstract
This paper describes an ultra-compact all-digital
multiplying delay-locked loop (MDLL) featuring a low-power
block-sharing offset-free freque ncy-tracking loop (FTL) to cali-
brate the process–voltage–temperature variations of the voltage-
controlled oscillator (VCO) frequency. Such FTL utilizes a
digital-controlled delay line (DCDL)-based low-power time-
interval comparator and an adjacent-edge selector, to precisely
detect the static phase offset (SPO) caused by the VCO frequency
drifting in t