JSSC 2019第1期RF & WirelessPLLEqualizer

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking Young-Ju Kim , Hye-Jung Kwon, Su-Yeon Doo, Minsu Ahn, Yong-Hun Kim, Yong-Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-Hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyungbae Park, Seunghoon Oh, Sang-Yong Lee, Ji-Hak Yu, Kihun Yu, Chulhee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yongjun Kim, Young-Hun Seo, Chang-Ho Shin, Chan-Yong Lee, Sam-Young Bang, Younsik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, and

16Gb GDDR6 DRAM采用每比特可训练单端DFE和ZQ编码发射器，实现18Gbps/pin高速操作

16 Gb/s/pin @1.15V, 18 Gb/s/pin @1.35V

GDDR6DRAM决策反馈均衡器高速接口信号完整性

▸每比特可训练单端决策反馈均衡器(DFE)

▸参考阻抗(ZQ)编码发射器

▸无锁相环(PLL)时钟技术

Abstract

The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to over- come I/O speed limitation by the DRAM process. Furthermore, this paper optimizes clock- and power-domain crossings and adopts split-die architecture to improve signal integrity (SI). This GDDR6 operates 16 Gb/s/pin with 1.15 V and achieves 18 Gb/s/pin with 1.35 V in the DRAM process.