JSSC 2019第1期Memory10nmSRAM

A 236-Mb per mm2 SRAM in 10-nm FinFET Technology With Pulse-pMOS TVC and Stepped

10nm FinFET技术中采用脉冲pMOS TVC和阶梯字线技术的高密度SRAM设计

23.6-Mb/mm2和20.4-Mb/mm2 SRAM阵列，0.6-V VMIN

SRAMFinFET写入辅助瞬态电压崩溃阶梯字线

▸脉冲pMOS瞬态电压崩溃（PP-TVC）写入辅助电路

▸阶梯字线（S-WL）技术

▸高密度和低电压6T SRAM位单元设计

Abstract

A 23.6-Mb/mm2 and a 20.4-Mb/mm2 SRAM arrays are manufactured in a 10-nm FinFET CMOS technology, utilizing high-density 0.0312 µm2 and low-voltage 0.0367 µm2 6T SRAM bitcells. A pulsed-pMOS transient voltage collapse (PP-TVC) write assist circuit is implemented to minimize write energy overhead of the TVC write assist technique, delivering 43% write energy reduction compared to the conventional strong-bias nMOS TVC (SBN-TVC). PP-TVC also achieves up to 50-mV write V MIN reduction at 90th percenti