JSSC 2019第1期Power Management65nmLDOVCO

A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltag

提出一种基于65nm CMOS工艺的全集成数字低压差稳压器，采用拍频量化器和自适应采样技术实现快速响应与低功耗

65nm CMOS, 0.6-1.2V输入, 0.4-1.1V输出, 100mA负载, 99.5%峰值效率

数字低压差稳压器拍频量化器自适应采样主动电压定位时间量化

▸使用压控振荡器和时间量化器替代传统电压量化器

▸采用拍频生成器作为采样时钟实现可变采样频率

▸内置主动电压定位技术降低瞬态电压偏差

Abstract

This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-fr equency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-ﬂip-ﬂop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast respons