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An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrat
14纳米三栅CMOS工艺中集成电压调节器的节能GPU原型，实现动态电压频率调整和能效优化。
14-nm Tri-Gate CMOS, 32% energy reduction at constant performance
图形处理器能效优化动态电压频率调整14纳米工艺集成电压调节器
▸集成电压调节器（IVR）
▸快速细粒度动态电压频率调整（DVFS）
▸每执行单元（EU）的V_MIN优化
Abstract
Graphics workloads make highly dynamic use
of resources such as execution units (EUs), and thus can
benefit from fast, fine-grain dynamic voltage and frequency
scaling (DVFS) and retentive sleep. This paper presents a 14-nm
graphics processing unit (GPU) prototype with modified EUs
which include an integrated voltage regulator (IVR). The IVR
enables energy-efficient EU turbo operation, data retention, and
V
MIN optimization per EU. Silicon measurements show that
IVR-enabled EU turbo operation offers