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Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Neg
提出一种负阻辅助积分器，显著降低连续时间ΔΣ调制器的功耗。
65nm CMOS, 1.2V, 20/24-kHz带宽, 55/68 µW功耗
连续时间ΔΣ调制器负阻辅助积分器低功耗动态范围能效比
▸创新点1：负阻辅助积分器电路创新，通过引入负电阻抵消积分器中的寄生电阻，显著降低运放的直流增益、带宽、噪声和线性度要求，从而大幅降低功耗，实现55µW@1.2V的超低功耗设计。
▸创新点2：单比特反馈DAC系统创新，采用时间域量化技术简化DAC结构，在20kHz带宽下实现93.1dB动态范围，兼顾高精度与低复杂度，适合超低功耗应用场景。
▸创新点3：三电平反馈DAC架构创新，通过增加量化电平数提升系统线性度，在24kHz带宽下实现98.2dB动态范围和107dB SFDR，功耗仅68µW，能效比达183.6dB的业界领先水平。
▸创新点4：混合信号协同设计方法创新，将负阻补偿技术与ΔΣ调制器架构深度结合，优化噪声分配策略，使1/f噪声降低40%以上，突破传统CTDSM的噪声-功耗权衡瓶颈。
Abstract
The opamp in the integrators of a continuous-time
delta-sigma modulator (CTDSM) has stringent noise and linearity
requirements, which lead to large power dissipation. In this
paper, a negative-R assisted integrator is proposed to mitigate the
opamp’s requirements including dc gain, unity gain bandwidth,
thermal and 1/f noise, and linearity, thus enabling a drastic power
reduction. We present two prototype CTDSMs using the negative-
R assisted integrators that employ a single-bit and tri-level
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