Capacitorless Self-Clocked All-Digital Low-Dropout Regulator

Abstract

This paper presents a capacitorless self-clocked digital low-dropout (SC-DLDO) regulator with self-shifting bidi- rectional shift registers (SS-BiSHRs) for power management applications in a system-on-chip (SoC). The load transient response is accelerated by utilizing coarse-then-fine control. Our voltage-range detector ensures accurate transition between coarse and fine loops without glitches or spikes in the output voltage. Moreover, the proposed SS-BiSHRs reduce the transient response time while minimizing the voltage under/overshoot. In addition, we propose a unary–binary segmentation (UBS) scheme of the power transistors. The UBS scheme offers a good balance between speed and resolution of the switch array. The proposed SC-DLDO fabricated on a 65-nm CMOS process with an active area of 0.069 mm 2 achieves a minimum dropout voltage of 40 mV or less at the input voltage of 0. 7–1.2 V . The measurement results show that with the step load current alternating between 1 and 90 mA, the proposed capacitorless SC-DLDO shows a transient response time of 77 ns with an undershoot of 96 mV at a regulated output voltage of 0.66 V and it attains the peak current and power efficiencies of 99.86% and 94.16%, respectively.