← 返回 JSSC 论文列表JSSC 2019第1期Power Management65nmLDO
Capacitorless Self-Clocked All-Digital Low-Dropout Regulator
一种无电容自时钟数字低压差稳压器,采用自移位双向移位寄存器加速瞬态响应。
65nm CMOS, 0.7-1.2V, 77ns瞬态响应时间, 96mV下冲, 99.86%峰值电流效率, 94.16%峰值功率效率
数字低压差稳压器自时钟无电容瞬态响应功率管理
▸自移位双向移位寄存器(SS-BiSHRs)
▸粗调后细调控制策略
▸单位-二进制分段(UBS)功率晶体管方案
Abstract
This paper presents a capacitorless self-clocked
digital low-dropout (SC-DLDO) regulator with self-shifting bidi-
rectional shift registers (SS-BiSHRs) for power management
applications in a system-on-chip (SoC). The load transient
response is accelerated by utilizing coarse-then-fine control.
Our voltage-range detector ensures accurate transition between
coarse and fine loops without glitches or spikes in the output
voltage. Moreover, the proposed SS-BiSHRs reduce the transient
response time whil