← 返回 JSSC 论文列表JSSC 2019第1期Clocking & PLLs65nmCrystal Oscillator
Design of Crystal-Oscilla tor Frequency Quadrupler for Low-Jitter
设计了一种基于晶体振荡器的频率四倍器，用于低抖动时钟乘法器，实现了216MHz参考时钟和77fs rms的集成抖动。
65nm CMOS, 1.0V, 6.5mW, 366fs rms抖动
晶体振荡器频率四倍器低抖动时钟乘法器数字校正
▸创新点1：晶体振荡器频率四倍器设计（电路创新），通过创新的电路架构将标准晶体振荡器频率提升至四倍（54MHz至216MHz），解决了高频低噪声参考时钟生成难题，同时保持77fs rms的低抖动性能。
▸创新点2：数字校正技术降低抖动（方法创新），采用先进的数字校正算法动态补偿相位误差，显著抑制高频倍频过程中的抖动累积，实现216MHz下77fs rms的业界领先指标。
▸创新点3：基于环形振荡器的注入锁定时钟乘法器（系统创新），通过四级联注入锁定环结构将216MHz参考时钟倍频至4.752GHz，系统级优化使得总功耗仅6.5mW（其中四倍器占1.5mW），面积0.16mm²。
▸创新点4：65nm CMOS工艺集成方案（工艺创新），在1.0V超低电压下实现全系统集成，四倍器与乘法器协同设计达成366fs rms@4.752GHz的综合性能，功耗效率优于同类方案。
Abstract
Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77fs rms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadru- pler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm 2 and achieves 366fsrms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.